april 2013 - revised november 2013 speci cations are subject to change without notice. the device characteristics and parameters in this data sheet can and do vary in different applications and actual device performance may vary over time. users should verify actual device performance in their speci c applications. tisp9110mdm overvoltage protector tisp9110mdm integrated complementary buffered-gate scrs for dual polarity slic overvoltage protection device symbol high performance protection for slics with +ve and -ve battery supplies ?wide -110 v to +110 v programming range ?low 5 ma max. gate triggering current ?dynamic protection performance speci ed for international surge waveshapes applications include: ?wireless local loop ?access equipment ?regenerated pots ?voip applications rated for international surge wave shapes how to order 8-soic (210 mil) package (top view) description the model tisp9110mdm is a programmable overvoltage protection device designed to protect modern dual polarity supply rail ringing slics (subscriber line interface circuits) against overvoltages on the telephone line. overvoltages can be caused by lightning, a.c. power contact and induction. four separate protection structures are used; two positive and two negative to provide optimum protection during metallic (differential) and longitudinal (common mode) protection conditions in both polar- ities. dynamic protection performance is speci ed under typical international surge waveforms from telcordia gr-1089-core, itu-t k.44 and yd/t 950. wave shape standard i ppsm a 2/10 gr-1089-core 150 10/700 itu-t k.20/21/45 80 10/1000 gr-1089-core 50 md-8soic(210)-003-a nc - no internal connection terminal typical application names shown in parenthesis 1 2 3 45 6 7 8 nc ground ground nc (-v (bat) ) g1 (tip or ring) line (ring or tip) line (+v (bat) ) g2 sd-tisp9-001- a g2 g1 ground line line the model tisp9110mdm is programmed by connecting the g1 and g2 gate terminals to the negative (-v (bat) ) and positive (+v (bat) ) slic battery supplies respectively. this creates a protector operating at typically +1.4 v above +v (bat) and -1.4 v below -v (bat) under a.c. power induction and power contact conditions. the protector gate circuitry incorporates 4 separate buffer transistors designed to provide independent control for each protection element. the gate buffer transistors minimize supply regulation issues by reducing the gate current drawn to around 5 ma, while the high voltage base emitter struct ures eliminate the need for expensive reverse bias protection gate diodes. the model tisp9110mdm is rated for common surges contained in regulatory requirements such as itu-t k.20, k.45, telcordia gr-10 89- core, yd/t 950. with the use of appropriate overcurrent protection devices such as the bourns multifuse and telefuse devices, circuits can be designed to comply with modern telecom standards. *rohs directive 2002/95/ec jan. 27, 2003 including annex and rohs recast 2011/65/eu june 8, 2011. device package carrier marking code standard quantity tisp9110mdm 8-soic (210 mil) embossed tape reeled TISP9110MDMR-S 9110m 2000 order as *rohs com pliant
april 2013 - revised november 2013 speci cations are subject to change without notice. the device characteristics and parameters in this data sheet can and do vary in different applications and actual device performance may vary over time. users should verify actual device performance in their speci c applications. absolute maximum ratings, t a = 25 ? (unless otherwise noted) tisp9110mdm overvoltage protector electrical characteristics for any section, t a = 25 ? (unless otherwise noted) parameter test conditions min typ max unit i d off-state current v d = v drm , v g1(line) = 0, v g2 +5 v v d = v drm , v g2(line) = 0, v g1 -5 v t a = 25 c t a = 85 c t a = 25 c t a = 85 c -5 -50 +5 +50 a i g1(line) negative-gate leakage current v g1(line) = -220 v - 5 a i g2(line) positive-gate leakage current v g2(line) = +220 v + 5 a v g1l(bo) gate - line impuls e breakover voltage v g1 = -100 v, i t = -100 a (see note 6) v g1 = -100 v, i t = -30 a 2/10 s 10/1000 s -15 -11 v v g2l(bo) gate - line impuls e breakover voltage v g2 = +100 v, i t = +100 a (see note 6) v g2 = +100 v, i t = +30 a 2/10 s 10/1000 s +15 +11 v i h - negative holding current v g1 = -60 v, i t = -1 a, di/dt = 1 a/ms -150 ma i g1t negative-gate trigger current i t =-5a, t p(g) 20s, v g1 = -60 v + 5 ma i g2t positive-gate trigger current i t =5a, t p(g) 20s, v g2 = 60 v - 5 ma c o line - ground off-state capacitance f = 1 mhz, v d = -3 v, g1 & g2 open circuit 33 pf note: 6. voltage measurements should be made with an oscillosc ope with limited bandw idth (20 mhz) to avoid high frequency no ise. rating symbol value unit repetitive peak off-state voltage v g1(line) =0, v g2 +5 v v g2(line) =0, v g1 -5 v v drm -120 +120 v non-repetitive peak impulse current (see notes 1, 2, 3 and 4) i ppsm 150 80 50 a 2/10 s (telcordia gr-1089-core) 5/310 s (itu-t k.20, k.21 & k.45, k.44 open-circuit voltage wave shape 10/700 ms) 10/1000 s (t elcordia gr-1089-core) non-repetitive peak on-state current, 50 hz / 60 hz (see notes 1, 2, 3 and 5) i tsm 9.0 5.0 1.7 a 0.2 s 1 s 900 s maximum negative battery supply voltage v g1m -110 v maximum positive battery supply voltage v g2m +110 v maximum differential battery supply voltage v (bat)m 220 v junction temperature t j -40 to +150 c storage temperature range t stg -65 to +150 c notes: 1. initially the device must be in thermal equilibrium with t j = 25 c. the surge may be repeated after the device returns to its initial conditions. 2. the rated current values may be applied to either of the line to ground terminal pairs. additionally, both terminal pairs ma y have their rated current values applied simultaneously (in this case the ground terminal current will be twice the rated current val ue of a single terminal pair). 3. rated currents only apply if pins 6 & 7 (ground) are connected together. 4. applies for the following bias conditions: v g1 = -20 v to -110 v, v g2 = 0 v to +110 v. 5. eia/jesd51-2 environment and eia/jesd51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths.
april 2013 - revised november 2013 speci cations are subject to change without notice. the device characteristics and parameters in this data sheet can and do vary in different applications and actual device performance may vary over time. users should verify actual device performance in their speci c applications. thermal characteristics, t a = 25 ? (unless otherwise noted) parameter measurement information tisp9110mdm overvoltage protector parameter test conditions min typ max unit r ja junction to ambient thermal resistance eia/jesd51-7 pcb, eia/jesd51-2 environment, p tot = 4 w (see note 7) 55 c/w note 7. eia/jesd51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths. figure 1. voltage-current characteristic unless otherwise noted, all voltages are referenced to the ground terminal quadrant iii switching characteristic -v v g1 v d i h i trm i ppsm v (bo) +i -i i d pm-tisp9-001-a i tsm v g2 v d v (bo) i h i trm i ppsm quadrant i switching characteristic i d +v i tsm
april 2013 - revised november 2013 speci cations are subject to change without notice. the device characteristics and parameters in this data sheet can and do vary in different applications and actual device performance may vary over time. users should verify actual device performance in their speci c applications. typical characteristics tisp9110mdm overvoltage protector figure 2. figure 3. off-state capacitance vs off-state voltag e v d - off-state voltage - v 0.1 1 10 100 c o - off-state capacitance - pf 10 15 20 30 35 40 45 25 50 tc-tisp9-001-a t j = 25 c v d = 1 vrms non-repetitive peak on-state current vs current duration t - current duration - s 0.1 1 10 100 1000 i tsm(t) - non-repetitive peak on-state current - a 1.5 2 3 4 5 6 7 8 9 15 1 10 ti-tisp9-001-a v gen = 600 vrms, 50/60 hz r gen = 1.4*v gen /i tsm(t) eia/jesd51-2 environment eia/jesd51-7 pcb, t a = 25 c simultaneous operation of r and t terminals. ground terminal current = 2 x i tsm(t) thermal information
april 2013 - revised november 2013 speci cations are subject to change without notice. the device characteristics and parameters in this data sheet can and do vary in different applications and actual device performance may vary over time. users should verify actual device performance in their speci c applications. tisp9110mdm overvoltage protector applications information slic -v bat slic protector tisp9110mdm c1 220 nf tip ring d1 c2 220 nf +v bat overcurrent protection figure 4. typical application diagram gr-1089-core intra building overcurrent protection 1 f1b b0500t f1a b0500t itu-t k.20 (basic) overcurrent protection 2 mf-sm013-250 + t mf-sm013-250 + t itu-t k.20 (enhanced 10/700 s 4 kv) overcurrent protection 3 *55 cptc *55 cptc + t + t * speci?c cptc can withstand 10/700 4 kv without primary protector. figure 5. typical overcurrent protection ?isp?is a registered trademark of bourns ltd., a bourns company, in the united states and other countries, except that ?isp is a registered trademark of bourns, inc. in china. ?ourns?is a registered trademark of bourns, inc. in the u.s. and other countries.
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